Yuan Taur

Yuan Taur
陶 元
Born (1946-09-27) September 27, 1946
Jiangxi, China
OccupationsElectrical engineer and academic
Academic background
EducationNational Taiwan University (BS)
University of California, Berkeley (PhD)
Academic work
InstitutionsUniversity of California, San Diego

Yuan Taur (Chinese: 陶元) (born September 27, 1946) is a Chinese American electrical engineer and academic. He is a Distinguished Professor Emeritus of Electrical and Computer Engineering (ECE) at the University of California, San Diego, where he taught from 2001 until his retirement in March 2025.[1]

Taur is known for his research in semiconductor device design and modeling, focusing on the structure and physics of transistors. He holds 14 U.S. patents and has authored or co-authored over 200 technical papers, in addition to coauthoring Fundamentals of Modern VLSI Devices with Tak Ning, spanning three editions released in 1998, 2009, and 2022.[2]

In 1998, Taur was elected as a Fellow of the IEEE. He served as Editor-in-Chief of the IEEE Electron Device Letters from 1999 to 2011.[3] He was the recipient of the IEEE Electron Devices Society's J. J. Ebers Award in 2012 "for contributions to the advancement of several generations of CMOS process technologies,"[4] and received the IEEE Electron Devices Society's Distinguished Service Award in 2014.[5]

Early life and education

Taur developed an early interest in mathematics during high school. At age 16, he achieved the highest score among all high school graduates in Taiwan on the united college entrance examination in 1963.[1][2][6]

He earned his B.S. degree in physics from National Taiwan University in Taipei, Taiwan, in 1967, and moved to the United States in 1968 to pursue doctoral study in physics at the University of California, Berkeley, completing his Ph.D. in 1974.[7]

Career

From 1974 to 1979, Taur worked as a research associate and postdoctoral researcher, first at the University of California, Berkeley, and then at the NASA Goddard Institute for Space Studies in New York.[1]

From 1979 to 1981, Taur held an appointment at the Rockwell International Science Center in Thousand Oaks, California, focusing on II-VI semiconductor devices for infrared sensor applications.[8]

From 1981 to 2001, he served in the Silicon Technology Department at IBM's Thomas J. Watson Research Center in Yorktown Heights, New York, holding the position of Manager of Exploratory Devices and Processes.[9]

In 2001, Taur joined the Jacobs School of Engineering at the University of California, San Diego as a professor in the Department of Electrical and Computer Engineering. He was appointed a Distinguished Professor in 2014, and retired from UCSD in March 2025, becoming Distinguished Professor Emeritus.[2][10]

Research

Taur is a semiconductor device design expert specializing in the structure and physics of transistors, with research spanning the CMOS scaling regime from 1 micrometer down to 10 nanometers. According to Google Scholar, he has an h-index of 66 across 298 publications.[1][3]

IBM research

While working at IBM T. J. Watson Research Center during 1981 to 2001, Taur's research focused on scaling CMOS transistors from 1 micron to 100 nm.[11] He investigated issues like avoiding CMOS latch-up, minimizing parasitic series resistance, gate work function for surface-channel pMOS, and shallow trench isolation process for achieving higher packing density. He also reported the first 100 nm CMOS transistors and published a conceptual super-halo design for 25 nm CMOS near the limit of bulk CMOS scaling.[12] In addition, he wrote an article on the limits to CMOS transistor scaling, listing factors like quantum mechanical tunneling through thin insulating layers, short-channel effect, standby power dissipation caused by injection of thermal electrons over a potential barrier.[13]

UCSD research

During his tenure at UCSD from 2001 to 2025, Taur's research has been mainly on the design and modeling of transistors from 100 nm to 10 nm.[2] He contributed to the field by publishing an analytic potential model for symmetric double-gate MOSFETs that remains continuous across all bias regions.[14] Additionally, he and his students published a series of papers on compact modeling of double-gate MOSFETs and nanowire transistors, a distributed model for oxide traps in III-V MOSFETs, and tunneling MOSFETs with a staggered source-channel heterojunction.[15][16][17] In 2019, he developed a non-GCA model capable of providing continuous solutions into the MOSFET saturation region, addressing limitations inherent in conventional models.[18]

Works

Taur's textbook, Fundamentals of Modern VLSI Devices coauthored with Tak H. Ning, has been widely used in first-year graduate courses on microelectronics worldwide. It has been translated into Japanese for all three editions and into Chinese for the 2nd and 3rd editions. This work delved into CMOS and bipolar VLSI devices, covering semiconductor physics, design optimization, power consumption, scaling, and physical limitations. The second edition elaborated on device parameter relationships, integrating MOSFET scale length theory, SiGe-base bipolar devices, and silicon-on-insulators, and included a chapter on VLSI memory devices, both volatile and non-volatile. Its third edition, published in 2022, expanded on modern VLSI device properties and designs, introducing about 25% new material on advancements like high-k gate dielectrics, double-gate MOSFETs, lateral bipolar transistors, and non-GCA MOSFET model.[19]

Awards and honors

  • 2012 – J. J. Ebers Award, IEEE Electron Devices Society[4]
  • 2014 – Distinguished Service Award, IEEE Electron Devices Society[5]
  • 2023 – Outstanding Alumnus Award, National Taiwan University

Bibliography

Books

  • Fundamentals of Modern VLSI Devices, 1st ed. (1998) ISBN 9780521559591
  • Fundamentals of Modern VLSI Devices, 2nd ed. (2009) ISBN 9780521832946
  • Fundamentals of Modern VLSI Devices, 3rd ed. (2022) ISBN 9781108480024

Selected articles

  • Taur, Y., Wind, S., Mii, Y. J., Lii, Y., Moy, D., Jenkins, K. A., ... & Polcari, M. (1993, December). High performance 0.1/spl mu/m CMOS devices with 1.5 V power supply. In Proceedings of IEEE International Electron Devices Meeting (pp. 127–130). IEEE.
  • Taur, Yuan, Douglas A. Buchanan, Wei Chen, David J. Frank, Khalid E. Ismail, Shih-Hsien Lo, George A. Sai-Halasz et al. "CMOS scaling into the nanometer regime." Proceedings of the IEEE 85, no. 4 (1997): 486–504.
  • Frank, D. J., Taur, Y., & Wong, H. S. (1998). Generalized scale length for two-dimensional effects in MOSFETs. IEEE Electron Device Letters, 19(10), 385–387.
  • Frank, D. J., Dennard, R. H., Nowak, E., Solomon, P. M., Taur, Y., & Wong, H. S. P. (2001). Device scaling limits of Si MOSFETs and their application dependencies. Proceedings of the IEEE, 89(3), 259–288.
  • Taur, Y., Liang, X., Wang, W., & Lu, H. (2004). A continuous, analytic drain-current model for DG MOSFETs. IEEE Electron Device Letters, 25(2), 107–109.
  • Taur, Y., Choi, W., Zhang, J., & Su, M. (2019). A non-GCA DG MOSFET model continuous into the velocity saturation region. IEEE Transactions on Electron Devices, 66(3), 1160–1166.

References

  1. 1 2 3 4 "Yuan Taur | Electrical and Computer Engineering". www.ece.ucsd.edu.
  2. 1 2 3 4 "Yuan Taur | Jacobs School of Engineering". jacobsschool.ucsd.edu.
  3. 1 2 "Yuan Taur - IEEE Electron Devices Society". IEEE.
  4. 1 2 "Past J.J. Ebers Award Winners - IEEE Electron Devices Society". IEEE.
  5. 1 2 "Distinguished Service Award Past Winners - IEEE Electron Devices Society". IEEE.
  6. ↑ "Yuan Taur scored highest in the unified college". Central Daily News. August 23, 1963.
  7. ↑ "Yuan Taur - IEEE Xplore".
  8. ↑ "Yuan Taur". IEEE.
  9. ↑ Taur, Yuan (2014). "Invited talk: CMOS device scaling — Past, present, and future". 2014 IEEE Workshop on Microelectronics and Electron Devices (WMED). p. 1. Bibcode:2014wmed.conf...13T. doi:10.1109/WMED.2014.6818711. ISBN 978-1-4799-2222-2.
  10. ↑ Deep, Aroon (2025-09-22). "Semiconductor designers chip in". The Hindu. ISSN 0971-751X. Retrieved 2026-06-23.
  11. ↑ Yuan Taur; Buchanan, D.A.; Wei Chen; Frank, D.J.; Ismail, K.E.; Shih-Hsien Lo; Sai-Halasz, G.A.; Viswanathan, R.G.; Wann, H.-J.C.; Wind, S.J.; Hon-Sum Wong (1997). "CMOS scaling into the nanometer regime". Proceedings of the IEEE. 85 (4): 486–504. Bibcode:1997IEEEP..85..486Y. doi:10.1109/5.573737.
  12. ↑ Taur, Y.; Wann, C.H.; Frank, D.J. (1998). "25 nm CMOS design considerations". International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217). pp. 789–792. doi:10.1109/IEDM.1998.746474. ISBN 0-7803-4774-9.
  13. ↑ Frank, D.J.; Dennard, R.H.; Nowak, E.; Solomon, P.M.; Taur, Y.; Hon-Sum Philip Wong (2001). "Device scaling limits of Si MOSFETs and their application dependencies". Proceedings of the IEEE. 89 (3): 259–288. Bibcode:2001IEEEP..89..259F. doi:10.1109/5.915374.
  14. ↑ Lu, Huaxin; Yu, Bo; Taur, Yuan (January 2008). "A unified charge model for symmetric double-gate and surrounding-gate MOSFETs". Solid-State Electronics. 52 (1): 67–72. Bibcode:2008SSEle..52...67L. doi:10.1016/j.sse.2007.06.018.
  15. ↑ Taur, Yuan; Song, Jooyoung; Yu, Bo (2008). "Compact modeling of multiple-gate MOSFETs". 2008 IEEE Custom Integrated Circuits Conference. pp. 257–264. doi:10.1109/CICC.2008.4672073. ISBN 978-1-4244-2018-6.
  16. ↑ Yuan, Yu; Wang, Lingquan; Yu, Bo; Shin, Byungha; Ahn, Jaesoo; McIntyre, Paul C.; Asbeck, Peter M.; Rodwell, Mark J. W.; Taur, Yuan (April 2011). "A Distributed Model for Border Traps in Al2O3−InGaAs MOS Devices". IEEE Electron Device Letters. 32 (4): 485–487. doi:10.1109/LED.2011.2105241.
  17. ↑ Yuan, Yu; Yu, Bo; Ahn, Jaesoo; McIntyre, Paul C.; Asbeck, Peter M.; Rodwell, Mark J. W.; Taur, Yuan (August 2012). "A Distributed Bulk-Oxide Trap Model for Al2O3 InGaAs MOS Devices". IEEE Transactions on Electron Devices. 59 (8): 2100–2106. doi:10.1109/TED.2012.2197000.
  18. ↑ Taur, Yuan; Choi, Woojin; Zhang, Jianing; Su, Meihua (2019). "A Non-GCA DG MOSFET Model Continuous into the Velocity Saturation Region". IEEE Transactions on Electron Devices. 66 (3): 1160–1166. Bibcode:2019ITED...66.1160T. doi:10.1109/TED.2019.2894685.
  19. ↑ "Fundamentals of modern VLSI devices | WorldCat.org". search.worldcat.org.
This page is issued from Wikipedia. The text is available under Creative Commons Attribution-Share Alike 4.0 unless otherwise noted. Additional terms may apply for the media files.